SR Latch

This module implements a SR NOR latch.

While s (set) and r (reset) are both low, q and q_n are maintained in a constant state, with q_n being the complement of q.If s goes high while r is held low, then q is forced high. Similarly, if r goes high while s is held low, then q is forced low. Having both s and r high (1) is a restricted combination.

Parameters

  • None

Ports

  • s set

  • r reset

  • q output

  • q_n complemented output

Source Code

sr_latch.sv
 1`ifndef LIBSV_LATCHES_SR_LATCH
 2`define LIBSV_LATCHES_SR_LATCH
 3
 4module sr_latch (
 5    input  logic                                     s,
 6    input  logic                                     r,
 7    output logic  /* verilator lint_off UNOPTFLAT */ q  /* verilator lint_on UNOPTFLAT */,
 8    output logic                                     q_n
 9);
10
11    assign q   = ~(r | q_n);
12    assign q_n = ~(s | q);
13
14endmodule
15
16`endif  /* LIBSV_LATCHES_SR_LATCH */