Binary Counter

This module implements a parameterized binary counter with an active-low asynchronous reset.

With every clock rising, the counter’s output q is incremented by 1. And with an assertion of the active-low reset, aresetn, q is set to 0.

Parameters

  • N number of bits

Ports

  • clk clock

  • aresetn asynchoronous active-low reset

  • q count (N bits)

Source Code

binary_counter.sv
 1`ifndef LIBSV_COUNTERS_BINARY_COUNTER
 2`define LIBSV_COUNTERS_BINARY_COUNTER
 3
 4module binary_counter #(
 5    parameter integer N  /* verilator public_flat_rd */ = 8
 6) (
 7    input  logic         clk,
 8    input  logic         aresetn,
 9    output logic [N-1:0] q
10);
11
12    always_ff @(posedge clk or negedge aresetn)
13        if (!aresetn) q <= 0;
14        else q <= q + 1;
15
16endmodule
17
18`endif  /* LIBSV_COUNTERS_BINARY_COUNTER */